RISC vs CISC / What is RISC and CISC Architecture?

What is RISC (Reduced instruction set computers) architechture.

RISC is a kind of microprocessor designed for the simultaneous execution of few instructions.  It can be done in less time as instructions are few. The use of fewer transistors which reduces its costs, is another benefit.

RISC technology is a central processing unit development approach based on the understanding that fundamental instruction set provides a high efficiency when coupled with a microprocessor architecture that is able to execute commands through the use of certain microprocessor cycles.

RISC instructions typically have less than 100 instructions and use 32 bits of fixed instructions. There are few easy methods of addressing. Register instructions are used which implies that the register is used for operations. LOAD / STORE are the only separate memory access instructions.

The instruction set in a RISC machine includes fundamental easy instructions that can compose more complicated instructions. Every intructions is identical in duration to be picked up in a single operation. Most of the instructions are in one cycle, allowing the processor to manage several commands simultaneously. This pipeline is a main technology for accelerating RISC machines.

RISC vs CISC / What is RISC and CISC Architecture?

What is CISC(Complex instruction set computers ) architechture

The set of CISC instructions includes approximately 120 to 350 instructions. It utilizes variable and data formats but a limited set of registries for particular purposes. The  large instruction sets is used because instructions are used in variable format. Many of the operations performed by a large number of memory reference modes are carried out.

Intel has developed the CISC. The CISC based computer will have shorter machine language programs.At the stage of assembly language, CISC provides a big amount of complicated orders. Memory was slow and costly during the early years, and programming was accomplished in assembly language. Because memory was slow, and commands could be recovered from a local ROM up to 10 times quicker than the primary memory, programmers attempted to include as much directions as feasible in a microcode.

A CISC is a computer where single instructions can execute countless low-level activities such as memory load, arithmetic operation, and memory store, or are performed in single instructions through multi-step procedures or addressing mode, as its name suggests "Complex Instruction Set."

It has a enormous amount of orders for compounding, which requires a long time to execute. Here, in several stages, a full range of orders is secured; each batch of orders has a further 300 distinct directions. Up to two to ten machine cycles complete the maximum directions. It is not easy to implement instruction pipelining at CISC.

Difference between RISC and CISC architechture

RISC has the design of divided information and instruction cache. In contrast, CISC utilizes a unified information cache, but recent designs also use divided caches.

In RISC with separate LOAD and STORE instructions, register-to-register memory mechanism is used. Alternatively, CISC utilizes memoryto memory for activities and combines LOAD and STORE directions.

The majority of the RISC CPU control is hardwired without the need of a control memory. Alternatively CISC is micro-coded and uses control memory , but also hardwired control is used in this time.

In RISC the size of the commands is low, and in the CISC the range of the commands is large.

A single clock and finite address mode is employed by RISC. Aternatively CISC utilizes 12 to 24 addressing modes.


 RISC is known as Reduced Instruction Set Computer.
CISC known as Complex Instruction Set Computer.
RISC processors takes simple instructions  about one clock cycle. 
CSIC processor takes complex instructions that  multiple clocks for execution
 In RISC more focus on software.
In CISC more focus on hardware.
 RISC has no memory unit 
CISC has memory unit.
It is highly pipelined.
It is not pipelined or less pipelined.
The Execution time of RISC is very less.
Execution time of CISC is very high.
In RISC Code expansion can be a problem.
In CISC Code expansion is not a problem.
In RISC Multiple register sets are present.
In CISC Only one  register set is present.
RISC supports complex addressing modes by using software.
CISC  supports complex addressing modes.
In RISC the Decoding of instructions is simple.
In CISC the Decoding of instructions is complex.
RISC architecture is used applications such as video processing, telecommunications and image processing.
CISC architecture is used applications such as security systems, home automation, etc.

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RISC and CISC Architecture? and do not forget to follow us on social sites for more intreasting facts.

RISC vs CISC / What is RISC and CISC Architecture?

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